; even- or odd-number ed parity by uartcr1) are added to the transfer data. the transfer data formats are shown as follows. figure 11-2 transfer data format figure 11-3 caution on ch anging transfer data format note: in order to switch the transfer data format, perform transmit operations in the above figure 11-3 sequence except for the initial setting. start bit 0 bit 1 bit 6 bit 7 stop 1 start bit 0 bit 1 bit 6 bit 7 stop 1 stop 2 start bit 0 bit 1 bit 6 bit 7 parity stop 1 start bit 0 bit 1 bit 6 bit 7 parity stop 1 stop 2 pe 0 0 1 1 stbt frame length 0 1 123 89101112 0 1 without parity / 1 stop bit with parity / 1 stop bit without parity / 2 stop bit with parity / 2 stop bit
page 111 TMP86C822UG 11.4 transfer rate the baud rate of uart is set of uartcr1. th e example of the baud rate are shown as follows. when tc5 is used as the uart transfer rate (when uartcr1 = ?110?), the tr ansfer clock and transfer rate are determined as follows: transfer clock [hz] = tc5 source clock [hz] / ttreg5 setting value transfer rate [baud] = transfer clock [hz] / 16 11.5 data sampling method the uart receiver keeps sampling input using the cloc k selected by uartcr1 until a start bit is detected in rxd pin input. rt clock star ts detecting ?l? level of the rxd pin. once a start bit is detected, the start bit, data bits, stop bi t(s), and parity bit are sampled at three times of rt7, rt8, and rt9 during one receiver clock interval (rt clock). (rt0 is the position where the bit supposedly starts.) bit is determined according to majority rule (the data are the same twice or more out of three samplings). figure 11-4 data sampling method table 11-1 transfer rate (example) brg source clock 16 mhz 8 mhz 4 mhz 000 76800 [baud] 38400 [baud] 19200 [baud] 001 38400 19200 9600 010 19200 9600 4800 011 9600 4800 2400 100 4800 2400 1200 101 2400 1200 600 rt0 1 2 3 4 5 6 7 8 9101112131415  01234567891011 bit 0 start bit bit 0 start bit (a) without noise rejection circuit rt clock internal receive data rt0 1 2 3 4 5 6 7 8 9101112131415  01234567891011 bit 0 start bit bit 0 start bit rt clock internal receive data (b) with noise rejection circuit rxd pin rxd pin
page 112 11. asynchronous serial interface (uart ) 11.6 stop bit length TMP86C822UG 11.6 stop bit length select a transmit stop bit length (1 bit or 2 bits) by uartcr1. 11.7 parity set parity / no parity by uartcr1 and set parity type (odd- or even-numbered) by uartcr1. 11.8 transmit/receive operation 11.8.1 data transmit operation set uartcr1 to ?1?. read uartsr to check ua rtsr = ?1?, then write data in tdbuf (transmit data buffer). writing data in tdbuf zero-cl ears uartsr, transfers the data to the transmit shift register and the data are sequenti ally output from the txd pin. the data output include a one-bit start bit, stop bits whose number is specified in uartcr1 and a parity bit if parity addition is specified. select the data transfer baud rate using uartcr1. when data transmit st arts, transmit buffer empty flag uartsr is set to ?1? a nd an inttxd interrupt is generated. while uartcr1 = ?0? and from when ?1? is written to uartcr1 to when send data are written to tdbuf, the txd pin is fixed at high level. when transmitting data, first read uartsr, then write data in tdbuf. otherwise, uartsr is not zero-cleared and transm it does not start. 11.8.2 data receive operation set uartcr1 to ?1?. when data are received vi a the rxd pin, the receive data are transferred to rdbuf (receive data buffer). at this time, the data transmitted includes a start bit and stop bit(s) and a parity bit if parity addition is specified. when stop bit(s) are received, data only are extracted and transferred to rdbuf (receive data buffer). then the receive buffer full flag ua rtsr is set and an intrxd interrupt is generated. select the data transfer baud rate using uartcr1. if an overrun error (oerr) occurs when data are received, the da ta are not transferre d to rdbuf (receive data buffer) but discarded; data in the rdbuf are not affected. note:when a receive operation is disabled by setting ua rtcr1 bit to ?0?, the setting becomes valid when data receive is completed. however, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs , be sure to perform a re-receive operation.
page 113 TMP86C822UG 11.9 status flag 11.9.1 parity error when parity determined using the receive data bits differs from the received parity bit, the parity error flag uartsr is set to ?1?. the uartsr is cl eared to ?0? when the rdbuf is read after read- ing the uartsr. figure 11-5 generation of parity error 11.9.2 framing error when ?0? is sampled as the stop bit in the receive data, framing error flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the rdbuf is r ead after reading the uartsr. figure 11-6 generati on of framing error 11.9.3 overrun error when all bits in the next data are received while unread data are still in rdbuf, overrun error flag uartsr is set to ?1?. in this case, the receive data is discarded; data in rdbuf are not affected. the uartsr is cleared to ?0? when the rdbuf is read af ter reading the uartsr. parity stop shift register pxxxx0 * 1pxxxx0 xxxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears perr. final bit stop shift register xxxx0 * 0xxxx0 xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears ferr.
page 114 11. asynchronous serial interface (uart ) 11.9 status flag TMP86C822UG figure 11-7 generati on of overrun error note:receive operations are di sabled until the overrun error flag uartsr is cleared. 11.9.4 receive data buffer full loading the received data in rdbuf sets receive data buffer full flag uartsr to "1". the uartsr is cleared to ?0? when the rdbuf is read after reading the uartsr. figure 11-8 generation of receive data buffer full note:if the overrun error flag uartsr is set during the period between reading the uartsr and reading the rdbuf, it cannot be cleared by only reading the rdbuf. therefore, after reading the rdbuf, read the uartsr again to check whether or not the overrun er ror flag which should have been cleared still remains set. 11.9.5 transmit data buffer empty when no data is in the transmit buffer tdbuf, uartsr is set to ?1?, that is, when data in tdbuf are transferred to the transmit shift register and data transmit star ts, transmit data buffer empty flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the tdbuf is written after reading the uartsr. final bit stop shift register xxxx0 * 1xxxx0 yyyy xxx0 ** rxd pin uartsr intrxd interrupt after reading uartsr then rdbuf clears oerr. rdbuf uartsr final bit stop shift register xxxx0 * 1xxxx0 xxxx yyyy xxx0 ** rxd pin uartsr intrxd interrupt rdbuf after reading uartsr then rdbuf clears rbfl.
page 115 TMP86C822UG figure 11-9 generation of transmit data buffer empty 11.9.6 transmit end flag when data are transmitted and no data is in tdbuf (uartsr = ?1?), transmit end flag uartsr is set to ?1?. the uartsr is cleared to ?0? when the data transmit is stated after writing the tdbuf. figure 11-10 generation of transmit end flag and transmit data buffer empty shift register data write data write zzzz xxxx yyyy start bit 0 final bit stop 1xxxx0 ***** 1 * 1xxxx **** 1x ***** 1 1yyyy0 tdbuf txd pin uartsr inttxd interrupt after reading uartsr writing tdbuf clears tbep. shift register * 1yyyy *** 1xx **** 1x ***** 1 stop start 1yyyy0 bit 0 txd pin uartsr uartsr inttxd interrupt data write for tdbuf
page 116 11. asynchronous serial interface (uart ) 11.9 status flag TMP86C822UG
page 117 TMP86C822UG 12. synchronous serial interface (sio) the TMP86C822UG has a clocked-synchron ous 8-bit serial interface. serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. serial interface is connected to outside peripherl devices via so, si, sck port. 12.1 configuration figure 12-1 serial interface sio control / status register serial clock shift clock shift register 3 2 1 0 7 6 5 4 transmit and receive data buffer (8 bytes in dbr) control circuit cpu serial data output serial data input 8-bit transfer 4-bit transfer serial clock i/o buffer control circuit so si sck siocr2 siocr1 siosr intsio interrupt request
page 118 12. synchronous serial interface (sio) 12.2 control TMP86C822UG 12.2 control the serial interface is controlled by sio control registers (s iocr1/siocr2). the serial interface status can be determined by reading sio status register (siosr). the transmit and receive data buffer is controlled by the siocr2. th e data buffer is assigned to address 0f90h to 0f97h for sio in the dbr area, and can continuously transfer up to 8 words (bytes or nibbles) at one time. when the specified number of words has b een transferred, a buffer empty (in th e transmit mode) or a buffer full (in the receive mode or tran smit/receive mode) interrupt (intsio) is generated. when the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive mode, a fixed interval wait can be applied to the serial clock fo r each word transferred. four different wait times can be selected with siocr2. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: set sios to "0" and sioinh to "1" when setting the transfer mode or serial clock. note 3: siocr1 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. sio control register 1 siocr176543210 (0f98h) sios sioinh siom sck (initial value: 0000 0000) sios indicate transfer start / stop 0: stop write only 1: start sioinh continue / abort transfer 0: continuously transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 000: 8-bit transmit mode 010: 4-bit transmit mode 100: 8-bit transmit / receive mode 101: 8-bit receive mode 110: 4-bit receive mode except the above: reserved sck serial clock select normal1/2, idle1/2 mode slow1/2 sleep1/2 mode write only dv7ck = 0 dv7ck = 1 000 fc/2 13 fs/2 5 fs/2 5 001 fc/2 8 fc/2 8 - 010 fc/2 7 fc/2 7 - 011 fc/2 6 fc/2 6 - 100 fc/2 5 fc/2 5 - 101 fc/2 4 fc/2 4 - 110 reserved 111 external clock ( input from sck pin ) sio control register 2 siocr276543210 (0f99h) wait buf (initial value: ***0 0000)
page 119 TMP86C822UG note 1: the lower 4 bits of each buffer are used during 4-bit tr ansfers. zeros (0) are stored to the upper 4bits when receiving. note 2: transmitting starts at the lowest address. received data are also stored starting from the lowest address to the highest address. ( the first buffer address transmitted is 0f90h ). note 3: the value to be loaded to buf is held after transfer is completed. note 4: siocr2 must be set when the serial interface is stopped (siof = 0). note 5: *: don't care note 6: siocr2 is write-only register, whic h cannot access any of in read-modify-wri te instruction such as bit operate, etc. note 1: t f ; frame time, t d ; data transfer time note 2: after sios is cleared to "0", siof is cleared to "0" at the termination of transfer or the setting of sioinh to "1". figure 12-2 fr ame time (t f ) and data transfer time (t d ) 12.3 serial clock 12.3.1 clock source internal clock or external clock for the source clock is selected by siocr1. wait wait control always sets "00" except 8-bit transmit / receive mode. write only 00: t f = t d (non wait) 01: t f = 2t d (wait) 10: t f = 4t d (wait) 11: t f = 8t d (wait) buf number of transfer words (buffer address in use) 000: 1 word transfer 0f90h 001: 2 words transfer 0f90h ~ 0f91h 010: 3 words transfer 0f90h ~ 0f92h 011: 4 words transfer 0f90h ~ 0f93h 100: 5 words transfer 0f90h ~ 0f94h 101: 6 words transfer 0f90h ~ 0f95h 110: 7 words transfer 0f90h ~ 0f96h 111: 8 words transfer 0f90h ~ 0f97h sio status register siosr76543210 (0f99h) siof sef siof serial transfer operating status moni- tor 0: 1: transfer terminated transfer in process read only sef shift operating status monitor 0: 1: shift operation terminated shift operation in process td tf (output) s ck output
page 120 12. synchronous serial interface (sio) 12.3 serial clock TMP86C822UG 12.3.1.1 internal clock any of six frequencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin goes high when transfer starts. when data writing (in the transmit mo de) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wa it function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. note: 1 kbit = 1024 bit (fc = 16 mhz, fs = 32.768 khz) figure 12-3 automatic wait fu nction (at 4-bit transmit mode) 12.3.1.2 external clock an external clock connected to the sck pin is used as the serial clock. in this case, output latch of this port should be set to "1". to ensure shifting, a pulse width of at least 4 machine cycles is required. this pulse is needed for the shift operatio n to execute certainly. actually, there is necessary processing time for interrupting, writing, and reading. the minimum pulse is determined by setting the mode and the pro- gram. therfore, maximum transfer frequenc y will be 488.3k bit/sec (at fc=16mhz). figure 12-4 external clock pulse width table 12-1 serial clock rate normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 sck clock baud rate clock baud rate clock baud rate 000 fc/2 13 1.91 kbps fs/2 5 1024 bps fs/2 5 1024 bps 001 fc/2 8 61.04 kbps fc/2 8 61.04 kbps - - 010 fc/2 7 122.07 kbps fc/2 7 122.07 kbps - - 011 fc/2 6 244.14 kbps fc/2 6 244.14 kbps - - 100 fc/2 5 488.28 kbps fc/2 5 488.28 kbps - - 101 fc/2 4 976.56 kbps fc/2 4 976.56 kbps - - 110 - - - - - - 111 external external external external external external a 1 a 2 b 0 b 1 b 2 b 3 c 0 c 1 a 3 a c b a 0 pin (output) pin (output) written transmit data a utomat i ca ll y wait function sck so t sckl t sckh tcyc = 4/fc (in the normal1/2, idle1/2 modes) 4/fs (in the slow1/2, sleep1/2 modes) t sckl , t sckh > 4tcyc sck pin (output)
page 121 TMP86C822UG 12.3.2 shift edge the leading edge is used to transmit, a nd the trailing edge is used to receive. 12.3.2.1 leading edge transmitted data are shifted on the leading edge of the serial clock (falling edge of the sck pin input/ output). 12.3.2.2 trailing edge received data are shifted on the trailing edge of the serial clock (rising edge of the sck pin input/out- put). figure 12-5 shift edge 12.4 number of bits to transfer either 4-bit or 8-bit serial transfer can be selected. when 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. the upper 4 bits are cleared to ?0? when receiving. the data is transferred in sequence star ting at the least significant bit (lsb). 12.5 number of words to transfer up to 8 words consisting of 4 bits of data (4-bit serial tran sfer) or 8 bits (8-bit serial tr ansfer) of data can be trans- ferred continuously. the number of words to be transferred can be selected by siocr2. an intsio interrupt is generated when the specified number of words has been transferred. if the number of words is to be changed during transfer , the serial interface must be stopped before making the ch ange. the number of words can be changed during automatic-wa it operation of an internal clock. in this case, the serial interface is not required to be stopped. bit 1 bit 2 bit 3 * 321 3210 ** 32 *** 3 bit 0 shift register shift register bit 1 bit 0 bit 2 bit 3 0 *** **** 210 * 10 ** 3210 (a) leading edge (b) trailing edge * ; don?t care so pin si pin sck pin sck pin
page 122 12. synchronous serial interface (sio) 12.6 transfer mode TMP86C822UG figure 12-6 number of words to transfer (example: 1word = 4bit) 12.6 transfer mode siocr1 is used to select the tr ansmit, receive, or tr ansmit/receive mode. 12.6.1 4-bit and 8-bit transfer modes in these modes, firstly set the sio control register to the transmit mode, and then write first transmit data (number of transfer words to be transfer red) to the data buffer registers (dbr). after the data are written, the transmission is star ted by setting siocr1 to ?1?. the data are then output sequentially to the so pin in synchronous with th e serial clock, starting with the least significant bit (lsb). as soon as the lsb has been output, the data are transferred from the data buffer register to the shift register. when the final data bit has been transferred a nd the data buffer register is empty, an intsio (buffer empty) interrupt is generated to request the next transmitted data. when the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer regist er by the time the number of data words specified with the siocr2 has been transmitted . writing even one word of data can cels the automatic- wait; therefore, when transmitting two or more words, always write the ne xt word before transmission of the previous word is completed. note:automatic waits are also canceled by writing to a dbr not being used as a transmit data buffer register; there- fore, during sio do not use such dbr for other applications. for example, when 3 words are transmitted, do not use the dbr of the remained 5 words. when an external clock is used, the data must be writte n to the data buffer register before shifting next data. thus, the transfer speed is determin ed by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. the transmission is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in buffer empty interrupt service program. a 1 a 2 a 3 a 0 a 1 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 a 0 a 1 a 0 a 2 a 3 b 0 b 1 b 2 b 3 c 0 c 1 c 2 c 3 (a) 1 word transmit (b) 3 words transmit (c) 3 words receive so pin intsio interrupt intsio interrupt intsio interrupt so pin si pin sck pin sck pin sck pin
page 123 TMP86C822UG siocr1 is cleared, the operation will end after all bits of words are transmitted. that the transmission has ended can be determined from the status of siosr becau se siosr is cleared to ?0? when a transfer is completed. when siocr1 is set, the transmission is immediately ended and siosr is cleared to ?0?. when an external clock is used, it is also necessary to clear siocr1 to ?0? before shifting the next data; if siocr1 is not cleared before shift out, dummy data will be transmitted and the operation will end. if it is necessary to change the number of word s, siocr1 should be cleared to ?0?, then siocr2 must be rewritten after confirming that siosr has been cleared to ?0?. figure 12-7 transfer m ode (example: 8bit, 1word tr ansfer, internal clock) figure 12-8 transfer mode (example: 8b it, 1word transfer , external clock) a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr siosr a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a 0 dbr b a clear sios write (a) write (b) sck pin (input) so pin intsio interrupt siocr1 siosr siosr
page 124 12. synchronous serial interface (sio) 12.6 transfer mode TMP86C822UG figure 12-9 transmiiied data ho ld time at end of transfer 12.6.2 4-bit and 8- bit receive modes after setting the control registers to the receive mode , set siocr1 to ?1? to enable receiving. the data are then transferred to the shift register via the si pin in synchronous with the serial clock. when one word of data has been received, it is tran sferred from the shift register to the data buffer register (dbr). when the number of words specified w ith the siocr2 has been received, an intsio (buffer full) interrupt is generated to request that these data be read out. the da ta are then read from the data buffer registers by the interrupt service program. when the internal clock is used, and the previous data are not read from the data buffer register before the next data are received, the serial cloc k will stop and an automatic-wait will be initiated until the data are read. a wait will not be initiated if even one data word has been read. note:waits are also canceled by reading a dbr not being used as a received data buffer register is read; therefore, during sio do not use such dbr for other applications. when an external clock is used, the shift operation is synchronized with the extern al clock; therefore, the previous data are read before the next data are transferred to the data buffer register. if the previous data have not been read, the next data will not be transferred to th e data buffer register and th e receiving of any more data will be canceled. when an external clock is used, th e maximum transfer speed is determined by the delay between the time when the interrupt request is gene rated and when the data received have been read. the receiving is ended by clearing si ocr1 to ?0? or setting sio cr1 to ?1? in buffer full interrupt service program. when siocr1 is cleared, th e current data are transferred to the buffer. after siocr1 cleared, the receiving is ended at the ti me that the final bit of the data has been received. that the receiving has ended can be determined from the st atus of siosr. siosr is cleared to ?0? when the receiv- ing is ended. after confirmed the r eceiving termination, the final receiving data is read. when siocr1 is set, the receiving is immediately ended and si osr is cleared to ?0 ?. (the received data is ignored, and it is not required to be read out.) if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0? then siocr2 mu st be rewritten after confirming th at siosr ha s been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data recei ving, siocr2 must be rewritten before the received data is read out. note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. msb of last word t sodh = min 3.5/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 3.5/fs [s] (in the slow1/2, sleep1/2 modes) sck pin so pin siosr
page 125 TMP86C822UG figure 12-10 receive mode (example: 8b it, 1word transfer, internal clock) 12.6.3 8-bit trans fer / receive mode after setting the sio control register to the 8-bit transmit/recei ve mode, write the data to be transmitted first to the data buffer registers (dbr). after that, enable the transmit/receive by sett ing siocr1 to ?1?. when transmitting, the data are output from the so pin at leading edges of the serial clock. when receiving, the data are input to the si pin at th e trailing edges of the serial clock. wh en the all receive is enabled, 8-bit data are transferred from th e shift register to the data buffer regist er. an intsio interrupt is generated when the number of data words specified with the siocr2 has been transferred. usually, read the receive data from the buffer register in the interrupt service. the data buffer register is used for both transmitting and receiving; therefore, always write the data to be transmitted af ter reading the all received data. when the internal clock is used, a wait is initiated until the received data are read and the next transfer data are written. a wait will not be initiated if ev en one transfer data word has been written. when an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift oper- ation. when an external clock is us ed, the transfer speed is determined by the maximum delay between genera- tion of an interrupt request and the received data are read and the data to be transmitted next are written. the transmit/receive operatio n is ended by clearing siocr1 to ?0? or setting siocr1 to ?1? in intsio interrupt service program. when siocr1 is cleared, the current data ar e transferred to the buff er. after siocr1 cleared, the transmitting/ receiving is ended at the time that the fi nal bit of the data has been transmitted. that the transmitting/ receiving has ended can be determined from the status of siosr. siosr is cleared to ?0? when the transmitting/recei ving is ended. when siocr1 is set, the transmit/receive operation is immediately ended and siosr is cleared to ?0?. if it is necessary to change the number of words in external clock operation, siocr1 should be cleared to ?0?, then sio cr2 must be rewritten after confirmi ng that siosr has been cleared to ?0?. if it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/receive operation, siocr2 must be rewritten before reading and writing of the receive/transmit data. a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 dbr b a clear sios read out read out sck pin (output) si pin intsio interrupt siocr1 siosr siosr
page 126 12. synchronous serial interface (sio) 12.6 transfer mode TMP86C822UG note:the buffer contents are lost when the transfer mode is switched. if it should become necessary to switch the transfer mode, end receiving by cl earing siocr1 to ?0?, read the last data and then switch the trans- fer mode. figure 12-11 transfer / receive mode (examp le: 8bit, 1word transfe r, internal clock) figure 12-12 transmitted data hold ti me at end of tr ansfer / receive a 1 a 0 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 c 1 c 0 c 2 c 3 c 4 c 5 c b c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 clear sios dbr d a read out (c) write (a) read out (d) write (b) sck pin (output) so pin intsio interrupt siocr1 siosr siosr si pin bit 7 of last word bit 6 t sodh = min 4/fc [s] ( in the normal1/2, idle1/2 modes) t sodh = min 4/fs [s] (in the slow1/2, sleep1/2 modes) sck pin so pin siosr
page 127 TMP86C822UG 13. 8-bit ad converter (adc) the TMP86C822UG have a 8-bit successive approximation type ad converter. 13.1 configuration the circuit configuration of the 8-bit ad converter is shown in figure 13-1. it consists of control registers adccr1 and adccr2, converted value registers adcdr1 and adcdr2, a da converter, a sample-and-hold circuit, a comp arator, and a successive comparison circuit. figure 13-1 8-bit ad converter (adc) 3 4 8 8 ainds analog input multiplexer adrs r/2 r/2 r ack irefon ad conversion result register1,2 ad converter control register 1,2 adbf eocf intadc interrupt sain successive approximate circuit adccr2 adcdr1 adcdr2 adccr1  sample hold circuit 0 y to n s en shift clock da converter reference voltage analog comparator control circuit vdd ain1 ain4 vss
page 128 13. 8-bit ad converter (adc) 13.1 configuration TMP86C822UG 13.2 control the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels in which to perform ad conversion and controls the ad con- verter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and controls the connect ion of the da converter (ladder resistor network). 3. ad converted value register (adcdr1) this register is used to store the digital value after being converted by the ad converter. 4. ad converted value register (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input when ad converter stops (adcdr2 = ?0?). note 2: when the analog input is all use disabl ing, the adccr1 should be set to ?1?. note 3: during conversion, do not perform output instruction to ma intain a precision for all of the pins. and port near to analo g input, do not input intense signaling of change. note 4: the adrs is automatically cl eared to ?0? after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop or slow/sleep mode are started, ad conver ter control register 1 (adccr1) is all initialized and no data can be written in this register. therefore, to use ad conv erter again, set the adccr1 newly after returning to normal1 or normal2 mode. note 7: although adccr1 is initialized to "reserved val ue" after reset, set the suitable analog input channel when using ad converter. note 8: always set bit 5 in adccr1 to ?1? and set bit 6 in adccr1 to ?0?. ad converter control register 1 adccr1 (000eh) 76543210 adrs "0" "1" ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: ?
page 129 TMP86C822UG note 1: always set bit 0 in adccr2 to ?0? and set bit 4 in adccr2 to ?1?. note 2: when a read instruction for adccr2, bit 6 to 7 in adccr2 read in as undefined data. note 3: after stop or slow/sleep mode are started, ad conver ter control register 2 (adccr2) is all initialized and no data can be written in this register. therefore, to use ad conv erter again, set the adccr2 newly after returning to normal1 or normal2 mode. note 1: settings for ? ?
page 130 13. 8-bit ad converter (adc) 13.3 function TMP86C822UG 13.3 function 13.3.1 ad conveter operation when adccr1 is set to "1", ad conversion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1) and at the same time adcdr2 is set to ?1?, the ad conversion finished interrupt (intadc) is generated. adccr1 is automatically cleared after ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr to see that the conversion is completed or wait until the inte rrupt signal (intadc) is generated (e.g., interrupt han- dling routine). figure 13-2 ad c onverter operation 13.3.2 ad converter operation 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to table 13-1. ? choose irefon for da converter control. 3. after setting up 1. and 2. above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. adcdr1 status eocf cleared by reading conversion result conversion result read conversion result read adcdr2 intadc interrupt reading adcdr1 reading adcdr2 adcdr2 adccr1 first conversion result second conversion result indeterminate ad conversion start ad conversion start
page 131 TMP86C822UG 13.3.3 stop and slow m ode during ad conversion when the stop or slow mode is entered forcibly du ring ad conversion, the ad convert operation is sus- pended and the ad converter is initialized (adccr1 and adccr2 are initialized to initial value.). also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering stop or slow mode.) when restored from stop or slow mode, ad conversion is not automatically restarted, so it is necessary to restart ad conversion. note that since the analog reference voltage is automa tically disconnected, there is no possibility of current flowing into the analog reference voltage. example :after selecting the conversion time of 19.5 s at 16 mhz and the analog input channel ain3 pin, perform ad conversion once. after checking eocf, read the converted value and store the 8-bit data in address 009fh on ram. ; ain select : : : : ; before setting the ad converter register, set each port reg- ister suitably (for detail, see chapter of i/o port.) ld (adccr1), 00100011b ; select ain3 ld (adccr2), 11011000b ; select conversion time (312/fc) and operation mode ; ad convert start set (adccr1). 7 ; adrs = 1 sloop: test (adcdr2). 5 ; eocf = 1 ? jrs t, sloop ; result data read ld a, (adcdr1) ld (9fh), a
page 132 13. 8-bit ad converter (adc) 13.3 function TMP86C822UG 13.3.4 analog input volt age and ad conversion result the analog input voltage is corresponded to the 8-bit digital value converted by the ad as shown in figure 13-3. figure 13-3 analog i nput voltage and ad conv ersion result (typ.) 10 01h 02h 03h fdh feh ffh 2 3 253 254 255 256 analog input voltage ad conversion result 256
page 133 TMP86C822UG 13.4 precautions about ad converter 13.4.1 restrictions for ad conv ersion interrupt (intadc) usage when an ad interrupt is used, it may not be processed depending on program composition. for example, if an intadc interrupt request is generated while an inte rrupt with priority lower than the interrupt latch il15 (intadc) is being accepted, the int adc interrupt latch may be cleared without the intadc interrupt being processed. the completion of ad conversion can be detected by the following methods: (1) method not using the ad conversion end interrupt whether or not ad conversion is completed can be detected by monitoring the ad conversion end flag (eocf) by software. this can be done by polling eocf or monitoring eocf at regular intervals after start of ad conversion. (2) method for detecting ad conversion end while a lower-priority interrupt is being processed while an interrupt with priority lower than intadc is being processed, chec k the ad conversion end flag (eocf) and interrupt latch il15. if il15 = 0 and eocf = 1, call the ad conversion end interrupt processing routine with consideration given to push/pop operations . at this time, if an interrupt request with priority higher than intadc has been set, the ad conversion end interrupt processing routine will be executed first against the specified priority. if n ecessary, we recommend that the ad conversion end interrupt processing rou- tine be called after checking whether or not an interrupt request with priority higher than intadc has been set. 13.4.2 analog input pin voltage range make sure the analog input pins (ain1 to ain4) are used at voltages within vss below vdd. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 13.4.3 analog input shared pins the analog input pins (ain1 to ain4) are shared wi th input/output ports. when using any of the analog inputs to execute ad convers ion, do not execute in put/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input shared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 13.4.4 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 13-4. the higher the output imped- ance of the analog input source, more easily they are su sceptible to noise. therefor e, make sure the output impedance of the signal source in your design is 5 k ? or less. toshiba also reco mmends attaching a capacitor external to the chip.
page 134 13. 8-bit ad converter (adc) 13.4 precautions about ad converter TMP86C822UG figure 13-4 analog input equivalent ci rcuit and example of input pin processing da converter ainx analog comparator internal resistance allowable signal source impedance internal capacitance 5 k ? ?
page 135 TMP86C822UG 14. key-on wakeup (kwu) in the TMP86C822UG , the stop mode is released by not only p20( int5 / stop ) pin but also stop2 pin. when the stop mode is released by stop2 pin, the stop pin needs to be used. in details, refer to the following section " 14.2 control ". 14.1 configuration figure 14-1 key-on wakeup circuit 14.2 control stop2 pin can controlled by key-on wakeup control register (stopcr). it can be configured as enable/disable in 1-bit unit. when this pin is used for stop mode release, configure corresponding i/o pin to input mode by i/o port register beforehand. 14.3 function stop mode can be entered by setting up the system control register (syscr1), and can be exited by detecting the "l" level on stop2 pin, which are enabled by stopcr, for releasing stop mode (note1). also, the level of the stop2 pin can be confirmed by r eading corresponding i/o port data register, check stop2 pin "h" that is enabled by stopcr befo re the stop mode is startd (note2). note 1: when the stop mode released by the edge release mode (syscr1 = ?0?), inhibit input from stop2 pin by key-on wakeup control register (stopcr) or must be set "h" level into stop2 pin that is available input during stop mode. note 2: when the stop pin input is high or stop2 pin inputwhich is enabled by stopcr is low, executing an instruction which starts stop mode will not place in stop mode but instead will immediately start the release sequence (warm up). key-on wakeup control register stopcr76543210 (0f9ah) stop2 (initial value: ***0 ****) stop2 stop mode released by stop2 0:disable 1:enable write only stopcr int5 stop stop mode release signal (1:release) (0f9ah) stop2 stop2
page 136 14. key-on wakeup (kwu) 14.3 function TMP86C822UG note 3: stop pin doesn?t have the control register such as stopcr, so when stop mode is released by stop2 pin, stop pin also should be used as stop mode release function. note 4: in stop mode, key-on wakeup pin which is enabled as input mode (for releasing stop mode) by key-on wakeup control register (stopcr) may genarate the penet ration current, so the said pin must be disabled ad conversion input (analog voltage input). note 5: when the stop mode is released by stop2 pin, the level of stop pin should hold "l" level (figure 14-2). figure 14-2 priority of stop pin and stop2 pin table 14-1 release level (edge) of stop mode pin name release level (edge) syscr1="1" (note2) syscr1="0" stop "h" level rising edge stop2 "l" level don?t use (note1) stop pin a) stop release stop mode stop mode stop pin "l" b) release stop mode stop mode in case of stop2 stop2 pin
page 137 TMP86C822UG 15. lcd driver the TMP86C822UG has a driver and control circuit to dir ectly drive the liquid crystal device (lcd). the pins to be connected to lcd are as follows: 1. segment output port 23 pins (seg31 to seg9) 2. common output port 4 pins (com3 to com0) in addition, vlc pin is provided for the lcd power supply. the devices that can be directly driven is sel ectable from lcd of the following drive methods: 1. 1/4 duty (1/3 bias) lcd max 92 segments (8 segments 11 digits) 2. 1/3 duty (1/3 bias) lcd max 69 segments (8 segments 8 digits) 3. 1/3 duty (1/2 bias) lcd max 69 segments (8 segments 8 digits) 4. 1/2 duty (1/2 bias) lcd max 46 segments (8 segments 5 digits) 5. static lcd max 23 segments (8 segments 2 digits) 15.1 configuration figure 15-1 lcd driver com3 com0 vlc duty control fc/2 17 , fs/2 9 fc/2 14 fc/2 16 , fs/2 8 common driver dbr display data area display data select control timing control display data buffer register blanking control segment driver fc/2 15 to lcdcr to duty slf edsp lrse power switch and  bias, bleeder  resistance 7 6 5 4 3 2 1 0 seg9 seg31
page 138 15. lcd driver 15.1 configuration TMP86C822UG 15.2 control the lcd control register (lcdcr) cont rols the lcd driver. edsp specifies whether to enable the lcd display. if edsp is cleared to ?0? for blanking, the power switch for the vlc pin is turned off. so, the com pin and pin out- put selected with seg enter gnd level. note 1: the base-frequency (slf) source clock is swit ched between high and low frequencies by the syscr2 pro- gramming. the base frequency does not depend on the tbtcr programming. note 2: if the setting of syscr2is changed, be sure to turn off the lcd (clear edsp to ?0?) to avoid the output of incor- rect waveform. note 3: programming lrse properly according to the lcd panel used. as the lrse programming increases (lengthen the period of enabling of the low resistor), the drive capability becomes higher while the power dissipation increases. reversely, as the lrse programming decreases shorten the period of enabling of the low resistor, the drive capability becomes lower while the power consumption decreases. note 4: if the idle0, sleep0, or stop mode is activated when the display is enabled, lcdcr is automatically changed to ?0? to blank the display. lcd driver control register lcdcr (0027h) 76543210 edsp lrsel duty slf (initial value: 0000 0000) edsp lcd display control 0: blanking 1: enables lcd display (blanking is released) r/w lrse period selection of enabling (turn on) of the low bleeder resistor (for implementing appropriate lcd panel drive capability) normal1/2, idle/1/2 mode slow1/2, sleep1/2 mode slf setting slf setting 11 10 01 00 01 00 00: 2 6 /fc 2 7 /fc 2 8 /fc 2 9 /fc 1/fs 2/fs 01: 2 9 /fc 2 10 /fc 2 11 /fc 2 12 /fc 2 3 /fs 2 4 /fs 10: always enabling 11: reserved duty selection of driving methods 000: 1/4 duty (1/3 bias) 001: 1/3 duty (1/3 bias) 010: 1/3 duty (1/2 bias) 011: 1/2 duty (1/2 bias) 100: static 101: reserved 110: reserved 111: reserved slf selection of lcd frame fre- quency normal1/2, idle0/1/2 mode slow1/2, sleep1/2 mode 00: 01: 10: 11: fc/2 17 [hz] fc/2 16 fc/2 15 fc/2 13 fs/2 9 [hz] fs/2 8 reserved reserved
page 139 TMP86C822UG 15.2.1 lcd driving methods as for lcd driving method, 5 types can be selected by lcdcr. the driving method is initialized in the initial program according to the lcd used. note 1: f f : frame frequency note 2: v lcd : lcd drive voltage (= v dd ? v lcd ?v lcd 1/f f 1/f f v lcd ?v lcd data "1" data "0" 0 data "1" ?v lcd data "0" 0 (b) 1/3 duty (1/3 bias) data "1" data "0" 1/f f v lcd 0 (c) 1/3 duty (1/2 bias) (a) 1/4 duty (1/3 bias) v lcd ?v lcd data "1" data "0" 1/f f 0 (e) static ?v lcd data "1" data "0" 1/f f v lcd 0 (d) 1/2 duty (1/2 bias)
page 140 15. lcd driver 15.1 configuration TMP86C822UG 15.2.2 frame frequency frame frequency (f f ) is set according to driving method and base frequency as shown in the following table 15-1. the base frequency is selected by lcdcr acco rding to the frequency fc and fs of the basic clock to be used. note: fc: high-frequency clock [hz] note: fs: low-frequency clock [hz] table 15-1 setting of lcd frame frequency for high frequency clock (a) at the syscr2 = ?0?. slf base frequency [hz] frame frequency [hz] 1/4 duty 1/3 duty 1/2 duty static 00 (fc = 16 mhz) 122 163 244 122 (fc = 8 mhz) 61 81 122 61 01 (fc = 8 mhz) 122 163 244 122 (fc = 4 mhz) 61 81 122 61 10 (fc = 4 mhz) 122 163 244 122 (fc = 2 mhz) 61 81 122 61 11 (fc = 2 mhz) 122 162 244 122 (fc = 1 mhz) 61 81 122 61 table 15-2 setting of lcd frame frequency for low frequency clock (b) at the syscr2 = ?1?. slf base frequency [hz] frame frequency [hz] 1/4 duty 1/3 duty 1/2 duty static 00 (fs = 32.768 khz) 64 85 128 64 01 (fs = 32.768 khz) 128 171 256 128 1* reserved fc 2 17 -------- fc 2 17 -------- 4 3 -- - fc 2 17 -------- ? ? ? ? ? ? ? ? ? ? ? ?
page 141 TMP86C822UG 15.2.3 lcd drive voltage lcd driving voltage vlcd is given as potential difference vdd ? vlc between pins vdd and vlc. therefore, when the cpu voltage and lcd drive voltage are the same, vlc pin will be connected to vss pin. the lcd lights when the potential difference between segment output and common output is vlcd. other- wise it turns off. during reset, the power switch of lcd driver is automatically turned off, shutting off the vlc voltage. after reset, if the p*lcr register (*; port no.) fo r each port is set to ?1? with lcdcr = ?0?, a gnd level is output from the pin which can be used as segment. the power switch is turned on to supply vlc voltage to lcd driver by setting with lcdcr to ?1?. if the idle0, sleep0, or stop mode is activated , lcdcr is automati cally changed to ?0? to blank the display. to turn the disp lay back on after releasing from th e previous mode, set lcdcr to ?1? again. note:during reset, the lcd common outputs (com3 to com0) are fixed ?0? level. however, the multiplex port (input/output port or seg output is selectable) becomes high impedance. therefore, when the reset input is long remarkably, ghost problem may appear in lcd display. 15.2.4 adjusting the lcd panel drive capability the lcd panel drive capability can be adjusted by programming lcdcr. when the period of enabling of the low bleeder resistor is lengthened, th e drive capability becomes hi gher while the power con- sumption increases. reversely, when the period of enabli ng of the low bleeder resistor is shortened, the drive capability becomes lower while the power consumption d ecreases. if the drive capability is not enough, the lcd display might present a ghost problem. so, implem ent the optimum drive capability for the lcd panel used. the figure below shows the bleeder resistance timing and equivalent circuit for 1/4 duty and 1/3 bias. figure 15-3 bleeder resistance selection wit h lcdcr (for 1/ 4 duty and 1/3 bias) vdd vm1 vm2 vlcd frame frequency r lt r lt r lt r lt r lt when lcdcr "10b" r lt r ht r lt r ht r lt r ht r lt r ht r lt r ht when lcdcr = "00b" or "01b" (a) on timing for low bleeder resistance vm2 vm vdd r l r l r l r h r h r h vlc high/low resistance switching signal r h : high resistance r l : low resistance vlc (b) equivalent circuit for bleeder resistance r lt : period during which resistance r l is selected (time specified with lcdcr) r ht : period during which resistance r h is selected (time specified with lcdcr 4 ? time specified with lcdcr)
page 142 15. lcd driver 15.3 lcd display operation TMP86C822UG 15.3 lcd display operation 15.3.1 display data setting display data is stored to the display data area (addres s 0f84h to 0f8fh,12 bytes) in the dbr. the display data stored in the display data area is automatically r ead out and sent to the lcd driver by the hardware. the lcd driver generates the segment signal and common si gnal according to the displa y data and driving method. therefore, display patterns can be changed by only over writing the contents of display data area by the pro- gram. table 15-4 shows the correspondence between the display data area and seg/com pins. lcd light when display data is ?1? and turn off when ?0?. according to the driving method of lcd, the number of pixels which can be driven becomes different, and the number of bits in the display data area which is used to store display da ta also becomes different. therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the addresses not connected to lcd can be used to store general user process data (see table 15-3). note: ?: this bit is not used for display data 15.3.2 blanking blanking is enabled when lcd cr is cleared to ?0?. to blank the lcd display and turn it off, a gnd-level signal is output to the com pin and the port which can be used as the segment by setting of p*lcr register (*; port no.). at this time, the power switch of vlc pin is turned off. table 15-3 driving method and bit for display data driving methods bit 7/3 bit 6/2 bit 5/1 bit 4/0 1/4 duty com3 com2 com1 com0 1/3 duty ? com2 com1 com0 1/2 duty ? ? com1 com0 static ? ? ? com0 table 15-4 lcd display data area (dbr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0f84h seg9 reserved 0f85h seg11 seg10 0f86h seg13 seg12 0f87h seg15 seg14 0f88h seg17 seg16 0f89h seg19 seg18 0f8ah seg21 seg20 0f8bh seg23 seg22 0f8ch seg25 seg24 0f8dh seg27 seg26 0f8eh seg29 seg28 0f8fh seg31 seg30 com3 com2 com1 com0 com3 com2 com1 com0
page 143 TMP86C822UG 15.4 control method of lcd driver 15.4.1 initial setting figure 15-4 shows the flowchart of initialization. figure 15-4 initial se tting of lcd driver 15.4.2 store of display data generally, display data are prepared as fixed data in program memory (rom) and stored in display data area by load command. note:db is a byte data definition instruction. example :to operate a 1/4 duty lcd of 32 segments 4 com-mons at fr ame frequency fc/2 16 [hz], the period of enabling of the low bleeder resistor: 2 8 /fc ld (lcdcr), 00000001b ; sets lcd driving method, the period of enabling of low bleeder resistor and frame frequency. ld (p*lcr), 0ffh ; sets segment output control register. (*; port no.) : : : : ; sets the initial value of display data. ld (lcdcr), 10000001b ; display enable example :(1) to display using 1/4 duty lcd a numerical valu e which corresponds to the lcd data stored in data memory at address 80h (when pins com and seg are connected to lcd as in figure 15-5), display data become as shown in table 15-5. ld a, (80h) add a, table-$-7 ld hl, 0f85h ld w, (pc + a) ld (hl), w ret table: db 11011111b, 00000110b, 11100011b, 10100111b, 00110110b, 10110101b, 11110101b, 00010111b, 11110111b, 10110111b sets lcd driving method (duty). sets frame frequency (slf). selects period of enabling of low resistor (lrse). sets segment output control registers (p*lcr (*; port no.)) initialization of display data area. display enable (edsp) (releases from blanking.)
page 144 15. lcd driver 15.3 lcd display operation TMP86C822UG figure 15-5 example of com, seg pin connection (1/4 duty) example: (2) table 15-6 shows an example of display data which are displayed using 1/2 duty lcd in the same way as table 15-5. the connection between pins com and seg are the same as shown in figure 15-6. figure 15-6 example of com, seg pin connection table 15-5 example of display data (1/4 duty) no. display display data no. display display data 0 11011111 5 101 10101 1 00000110 6 11110101 2 11100011 7 00000111 3 10100111 8 11110111 4 00110110 9 10110111 seg10 seg11 com0 com1 com2 com3 seg10 seg12 seg11 seg13 com0 com1
page 145 TMP86C822UG note: *: don?t care 15.4.3 example of lcd driver output figure 15-7 1/4 duty (1/3 bias) drive table 15-6 example of display data (1/2 duty) number display data number display data high order address low order address high order address low order address 0 **01**11 **01**11 5 **11**10 **01**01 1 **00**10 **00**10 6 **11**11 **01**01 2 **10**01 **01**11 7 **01**10 **00**11 3 **10**10 **01**11 8 **11**11 **01**11 4 **11**10 **00**10 9 **11**10 **01**11 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lcd -v lcd v lcd 0 0 -v lcd seg10 seg11 display data area address 0f85 h seg10 edsp seg11 com0 com1 com2 com3 com0-seg10 (selected) com2-seg11 (non selected) 1011 0101 com0 com1 com2 com3
page 146 15. lcd driver 15.3 lcd display operation TMP86C822UG figure 15-8 1/3 duty (1/3 bias) drive seg12 address *: don?t care seg10 edsp seg11 seg12 com0 com1 com2 com0-seg11 (selected) com1-seg12 (non selected) seg11 seg10 com0 com1 com2 display data area 0f85 h 0f86 h *111 *010 **** *001 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lc 0 v lcd -v lcd v lcd 0 0 -v lcd
page 147 TMP86C822UG figure 15-9 1/3 duty (1/2 bias) drive seg12 address *: don?t care seg10 edsp seg11 seg12 com0 com1 com2 com0-seg11 (selected) com1-seg12 (non selected) seg11 seg10 com0 com1 com2 display data area 0f85 h 0f86 h *111 *010 **** *001 v dd v lc v dd v lc v dd v lc v dd v lc v dd v lc v dd v lc 0 0 v lcd v lcd -v lcd -v lcd
page 148 15. lcd driver 15.3 lcd display operation TMP86C822UG figure 15-10 1/2 duty (1/2 bias) drive seg13 address *: don?t care seg10 edsp seg11 seg12 seg13 com0 com1 com0-seg11 (selected) com1-seg12 (non selected) seg10 com0 display data area 0f85 h 0f86 h **01 **01 **11 **10 v dd v lc v dd v lc v dd v lc v dd v lc v dd v lc v dd v lc 0 seg11 seg12 com1 0 v lcd v lcd -v lcd -v lcd
page 149 TMP86C822UG figure 15-11 static drive seg12 seg17 address 0f85 h seg15 seg14 seg13 seg10 seg11 seg16 com0 v dd v dd vlc v dd vlc v dd v lcd -v lcd v lcd 0 seg10 seg14 seg17 com0 com0-seg10 (selected) com0-seg14 (non selected) 0 edsp 0f86 h 0f87 h 0f88 h ***0 ***1 ***1 ***1 ***1 ***0 ***0 ***1 display data area *: don?t care v lc vlc -v lcd
page 150 15. lcd driver 15.3 lcd display operation TMP86C822UG
page 151 TMP86C822UG 16. input/output circuit 16.1 control pins the input/output circuitries of the TMP86C822UG control pins are shown below. note: the test pin of tmp86ph22ug does not have a pull-down resistor. fix the test pin at low level. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins (high frequency) r f = 1.2 m ? ? ? ? ? ? ? ? fc r f r o osc.enable xin xout vdd vdd fs r f r o osc.enable xtin xtout vdd xten vdd address-trap-reset watchdog-timer-reset system-clock-reset r r in vdd r in r vdd
page 152 16. input/output circuit 16.2 input/output ports TMP86C822UG 16.2 input/output ports port i/o input/output circuitry remarks p1 i/o tri-stateo i/o hysteresis input r = 100 ? ? ? ? ? initial "high-z" disable data output seg output pin input vdd r output latch input initial "high-z" disable data output seg output pin input vdd r output latch input vdd r initial "high-z" data output disable output latch input pin input vdd r initial "high-z" data output disable output latch input pin input initial "high-z" disable data output pin input vdd r output latch input
page 153 TMP86C822UG p37 output sink open drain output high current output (nch) p61 to p64 i/o tri-stateo i/o hysteresis input r = 100 ? vdd initial "high-z" data output disable output latch input initial "high-z" disable data output pin input vdd r analog input key-on wakeup output latch input
page 154 16. input/output circuit 16.2 input/output ports TMP86C822UG
page 155 TMP86C822UG 17. electrical characteristics 17.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (v ss = 0 v) parameter symbol pins rating unit supply voltage v dd ? ? ? ? ? ? ?
page 156 17. electrical characteristics 17.2 recommended operating condition TMP86C822UG 17.2 recommended op erating condition the recommended operating co nditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is us ed under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the r ecommended operating conditions for the device are always adhered to. note 1: when the supply voltage is 1.8 v ? ?
page 157 TMP86C822UG 17.3 dc characteristics note 1: typical values show those at topr = 25 ? ? + ? ?
page 158 17. electrical characteristics 17.4 lcd characteristics TMP86C822UG 17.4 lcd characteristics note 1: output resistors r os and r oc indicate "on" when swiching levels. note 2: v o2/3 indicates the output voltage at 2/3 level when operating in the 1/4 or 1/3 duty mode. note 3: v o1/2 indicates the output voltage at 1/2 level when operating in the 1/2 or static duty mode. note 4: v o1/3 indicates the output voltage at 1/3 level when operating in the 1/4 or 1/3 duty mode. note 5: when using lcd, it is neces sary to consider values of r os1/2 and r oc1/2 . (v ss = 0 v, topr = ? ? ? ? ? ?
page 159 TMP86C822UG 17.5 ad conversi on characteristics note 1: the total error includes all errors except a quantizati on error, and is defined as ma ximum deviation from the ideal conversion line. note 2: conversion time is different in recommended value by power supply voltage. about conversion time, please refer to ?8-bit ad converter (adc)?. note 3: please use input voltage to ain input pin in limit of v dd ? ? 1 1 1 2 ? 1 1 1 2 ? ? 2 2 2
page 160 17. electrical characteristics 17.6 ac characteristics TMP86C822UG 17.6 ac characteristics note 1: when the supply voltage is 1.8 v ? ? ? ?
page 161 TMP86C822UG 17.7 timer counter 1 inpu t (ecin) characteristics (v ss = 0 v, topr = ?
page 162 17. electrical characteristics 17.8 recommended oscillating conditions TMP86C822UG 17.8 recommended osc illating conditions note 1: a quartz resonator can be used for high-frequency oscillation only when v dd is 2.7 v or above. if v dd is below 2.7 v, use a ceramic resonator. note 2: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will act ually be mounted. note 3: for the resonators to be used with toshiba microcontrollers, we recommend ceramic resonators manufactured by murata manufacturing co., ltd. for details, please visit the website of murata at the following url: http://www.murata.com 17.9 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition. (2) low-frequency oscillation (1) high-frequency oscillation xin xout c 2 c 1 xtin xtout c 2 c 1
page 163 TMP86C822UG 18. package dimension 0.37 12.0 0.2 10.0 0.2 12.0 0.2 10.0 0.2 0.6 0.15 0.25 0.145 0.055 0.1 1.6max 0.05 1.4 0.05 0.08 0.07 0.2 0.8 1.0typ p-lqfp44-1010-0.80b unit: mm
page 164 18. package dimension TMP86C822UG
this is a technical document that de scribes the operating functi ons and electrical specif ications of the 8-bit microcontroller series tlcs-870/c (lsi). toshiba provides a variety of development tools a nd basic software to enable efficient software development. these development tools have specifi cations that support advances in microcomputer hardware (lsi) and can be used extensively. both the hardware and so ftware are supported continuous ly with version updates. the recent advances in cmos lsi production technology have be en phenomenal and microcomputer systems for lsi design are constant ly being improved. the products described in this document may also be revised in the future. be sure to check the latest specific ations before using. toshiba is developing highly integrated, high-perfo rmance microcomputers using advanced mos production technology and especially well proven cmos technology. we are prepared to meet the requests for custom packaging for a variet y of application areas. we are confident that our products can satisfy your application needs now and in the future.